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cy7c1440av33 36-mbit (1 m 36) pipelined sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05383 rev. *k revised may 14, 2012 36-mbit (1 m 36) pipelined sync sram features supports bus operation up to 250 mhz available speed grades are 250 and 167 mhz registered inputs and outputs for pipelined operation 3.3 v core power supply 2.5 v/3.3 v i/o power supply fast clock-to-output times ? 2.6 ns (for 250-mhz device) provide high-performance 3-1-1-1 access rate user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable single cycle chip deselect cy7c1440av33 available in pb-free 100-pin tqfp package, pb-free 165-ball fbga package. ieee 1149.1 jtag-compatible boundary scan ?zz? sleep mode option functional description the cy7c1440av33 sram integrates 1 m 36 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. gw when active low causes all bytes to be written. the cy7c1440av33 operates from a +3.3 v core power supply while all outputs may operate with either a +2.5 or +3.3 v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide description 250 mhz 167 mhz unit maximum access time 2.6 3.4 ns maximum operating current 475 375 ma maximum cmos standby current 120 120 ma
cy7c1440av33 document number: 38-05383 rev. *k page 2 of 33 logic block diagram ? cy7c1440av33 address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver
cy7c1440av33 document number: 38-05383 rev. *k page 3 of 33 contents pin configurations ........................................................... 4 pin definitions .................................................................. 6 functional overview ........................................................ 7 single read accesses ................................................ 7 single write accesses initia ted by adsp ................... 7 single write accesses initiate d by adsc ................... 8 burst sequences ......................................................... 8 sleep mode ................................................................. 8 interleaved burst address tabl e ................................. 8 linear burst address table ......................................... 8 zz mode electrical characteri stics .............................. 8 truth table ........................................................................ 9 truth table for read/write ............................................ 10 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 11 disabling the jtag feature ...................................... 11 test access port (tap) ............................................. 11 performing a tap r eset .......... .............. .......... 11 tap registers ...................................................... 11 tap instruction set ................................................... 11 tap controller state diagram ....................................... 13 tap controller block diagram ...................................... 14 tap timing ...................................................................... 14 tap ac switching characteristics ............................... 15 3.3 v tap ac test conditions ....................................... 15 3.3 v tap ac output load equivalent ......................... 15 2.5 v tap ac test conditions ....................................... 15 2.5 v tap ac output load equivalent ......................... 15 tap dc electrical characteristics and operating conditions ..................................................... 16 identification register definitions ................................ 17 scan register sizes ....................................................... 17 instruction codes ........................................................... 17 boundary scan order .................................................... 18 maximum ratings ........................................................... 19 operating range ............................................................. 19 electrical characteristics ............................................... 19 capacitance .................................................................... 20 thermal resistance ........................................................ 20 ac test loads and waveforms ..................................... 20 switching characteristics .............................................. 21 switching waveforms .................................................... 22 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 package diagrams .......................................................... 27 acronyms ........................................................................ 29 document conventions ................................................. 29 units of measure ....................................................... 29 document history page ................................................. 30 sales, solutions, and legal information ...................... 33 worldwide sales and design s upport ......... .............. 33 products .................................................................... 33 psoc solutions ......................................................... 33
cy7c1440av33 document number: 38-05383 rev. *k page 4 of 33 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dqc v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1440av33 (1 m 36) nc a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a mode a
cy7c1440av33 document number: 38-05383 rev. *k page 5 of 33 figure 2. 165-ball fbga (15 17 1.4 mm) pinout pin configurations (continued) cy7c1440av33 (1 m 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss
cy7c1440av33 document number: 38-05383 rev. *k page 6 of 33 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [1] are sampled active. a1:a0 are fed to the two-bit counter. bw a , bw b , bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselec t the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. not available for aj package version. not connected for bga. where referenced, ce 3 is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted hi gh, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically incr ements the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserve d. for normal operation, this pin ha s to be low or left floating. zz pin has an internal pull-down. dqs, dqp x i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, t hey deliver the data contained in t he memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . note 1. x = ?don't care.? h = logic high, l = logic low.
cy7c1440av33 document number: 38-05383 rev. *k page 7 of 33 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. maximum access delay from the clock rise (t co ) is 2.6 ns (250-mhz device). the cy7c1440av33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller addre ss strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burs t counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplif ied with on-chip synchronous self-timed write circuitry. three synchronous ch ip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the rising e dge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, it s outputs are always tri-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will tri-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dqs inputs is written into the corresponding address location in the memory array. if gw is v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pin should be disconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disc onnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disc onnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to th e jtag circuitry . if the jtag feature is not being ut ilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die nc/72m, nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to the die. nc/72m, nc/144m, nc /288m, nc/576m and nc/1g are address expansion pins are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1440av33 document number: 38-05383 rev. *k page 8 of 33 high, then the write operation is controlled by bwe and bw x signals. the cy7c1440av33 provides by te write capability that is described in the write cycle descriptions table. asserting the byte write enable input (bwe ) with the selected byte write (bw x ) input, will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because cy7c1440av33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are automat ically tri-stated whenever a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is co nducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because cy7c1440av33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are automat ically tri-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1440av33 provides a two-bit wraparound counter, fed by a1:a0, that implements eit her an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to s upport processors that follow a linear burst sequence. the burs t sequence is user selectable through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 100 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ? ns
cy7c1440av33 document number: 38-05383 rev. *k page 9 of 33 truth table the truth table for cy7c1440av33 follows. [2, 3, 4, 5, 6, 7] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l?h tri-state deselect cycle, power-down none l l x l l x x x x l?h tri-state deselect cycle, power-down none l x h l l x x x x l?h tri-state deselect cycle, power-down none l l x l h l x x x l?h tri-state deselect cycle, power-down none l x h l h l x x x l?h tri-state sleep mode, power-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tri-state write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tri-state read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tri-state read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tri-state write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tri-state read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tri-state write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. bga package has only 2 chip selects ce 1 and ce 2 . 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sa mpled with the clock rise. it is masked interna lly during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and a ll data bits behave as output when oe is active (low).
cy7c1440av33 document number: 38-05383 rev. *k page 10 of 33 truth table for read/write the truth table for read/write for cy7c1440av33 follows. [8, 9, 10] function (cy7c1440av33) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? (dq a and dqp a )hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c )hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d )hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes hlllll write all bytes l x x x x x notes 8. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 9. bw x represents any byte write signal. to enable any byte write bw x , a logic low signal should be applied at clock rise. any number of bye writes can be enabled at the same time for any given write. 10. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active.
cy7c1440av33 document number: 38-05383 rev. *k page 11 of 33 ieee 1149.1 serial boundary scan (jtag) the cy7c1440av33 incorporates a serial boundary scan test access port (tap). this part is fully compliant with ieee standard 1149.1. the tap operates using jedec-standard 3.3 v or 2.5 v i/o logic levels. the cy7c1440av33 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which wil l not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram on page 13 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) of any register. test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 17 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset in ternally to ensure that tdo comes up in a high z state. tap registers registers are connected betwe en the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 14 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identification register definitions on page 17 . tap instruction set overview eight different instructions are possible with the three bit instruction register . all combinations are listed in the instruction codes on page 17 . three of these instru ctions are listed as reserved and should not be used. the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute
cy7c1440av33 document number: 38-05383 rev. *k page 12 of 33 the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to th e value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap co ntroller?s capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preloa d instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required ? that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system ou tput pins. this inst ruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at, bit #89 (for 165-ball fbga package). wh en this scan cell, called the ?extest output bus tri-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instructio n. when high, it will enable the output buffers to drive the ou tput bus. when low, this bit will place the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? state. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bus pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1440av33 document number: 38-05383 rev. *k page 13 of 33 tap controller state diagram the 0/1 next to each state represents t he value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1440av33 document number: 38-05383 rev. *k page 14 of 33 tap controller block diagram tap timing bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck tms tap controller tdi tdo t tl test clock (tck) 123456 test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
cy7c1440av33 document number: 38-05383 rev. *k page 15 of 33 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times....................................................1 ns input timing reference levels...... ............ ........................1.5 v output reference levels .................. ...............................1.5 v test load termination supply volt age ................ .............1.5 v 3.3 v tap ac out put load equivalent 2.5 v tap ac test conditions input pulse levels............................................... .v ss to 2.5 v input rise and fall time .....................................................1 ns input timing reference levels.... .............. ......................1.25 v output reference levels ........... ...... ..............................1.25 v test load termination supply voltage ................... ........1.25 v 2.5 v tap ac output load equivalent tap ac switchi ng characteristics over the operating range parameter [11, 12] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns set-up times t tmss tms set-up to tck clock rise 5 ? ns t tdis tdi set-up to tck clock rise 5 ? ns t cs capture set-up to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns tdo 1.5v 20pf z = 50 ? o 50 ? tdo 1.25v 20pf z = 50 ? o 50 ? notes 11. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 12. test conditions are sp ecified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1440av33 document number: 38-05383 rev. *k page 16 of 33 tap dc electrical characteristics and operating conditions (0 c < t a < +70 c; v dd = 3.135 to 3.6 v unless otherwise noted) parameter [13] description test conditions min max unit v oh1 output high voltage i oh = ?4.0 ma, v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma, v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3 v ? 0.4 v i ol = 1.0 ma v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.3 0.8 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 13. all voltages referenced to v ss (gnd).
cy7c1440av33 document number: 38-05383 rev. *k page 17 of 33 identification regi ster definitions instruction field cy7c1440av33 (1 m 36) description revision number (31:29) 000 describes the version number. device depth (28:24) [14] 01011 reserved for internal use architecture/memory type(23:18) 000000 de fines memory type and architecture bus width/density(17:12) 100111 defines width and density cypress jedec id code (11:1) 00000110100 allo ws unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. scan register sizes register name bit size (x 36) instruction 3 bypass 1 id 32 boundary scan order (165-ball fbga package) 89 instruction codes instruction code description extest 000 captures the i/o ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places th e boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. note 14. bit #24 is ?1? in the id register definitions for both 2.5 v and 3.3 v versions of this device.
cy7c1440av33 document number: 38-05383 rev. *k page 18 of 33 boundary scan order 165-ball fbga [15, 16] cy7c1440av33 (1 m 36) bit # ball id bit # ball id bit # ball id bit # ball id 1 n6 26 e11 51 a3 76 n1 2 n7 27 d11 52 a2 77 n2 3n10 28g10 53b2 78p1 4p11 29f10 54c2 79r1 5 p8 30 e10 55 b1 80 r2 6 r8 31 d10 56 a1 81 p3 7r9 32c11 57c1 82r3 8p9 33a11 58d1 83p2 9p10 34b11 59e1 84r4 10 r10 35 a10 60 f1 85 p4 11 r11 36 b10 61 g1 86 n5 12h11 37a9 62d2 87p6 13 n11 38 b9 63 e2 88 r6 14 m11 39 c10 64 f2 89 internal 15 l11 40 a8 65 g2 16 k11 41 b8 66 h1 17 j11 42 a7 67 h3 18 m10 43 b7 68 j1 19 l10 44 b6 69 k1 20 k10 45 a6 70 l1 21 j10 46 b5 71 m1 22 h9 47 a5 72 j2 23 h10 48 a4 73 k2 24 g11 49 b4 74 l2 25 f11 50 b3 75 m2 notes 15. balls that are nc (no connect) are preset low. 16. bit# 89 is preset high.
cy7c1440av33 document number: 38-05383 rev. *k page 19 of 33 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.3 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.3 v to +v dd dc voltage applied to outputs in tri-state ..........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................. ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range parameter [17, 18] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?? 4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?? 1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [17] for 3.3 v i/o 2.0 v dd + 0.3 v for 2.5 v i/o 1.7 v dd + 0.3 v v il input low voltage [17] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 a input current of mode input = v ss ?30 ? a input = v dd ?5a input current of zz input = v ss ?5 ? a input = v dd ?30a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz ?475ma 6-ns cycle, 167 mhz ?375ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc all speeds ? 225 ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 120 ma notes 17. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 18. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq ? v dd .
cy7c1440av33 document number: 38-05383 rev. *k page 20 of 33 i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, or v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc all speeds ? 200 ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 135 ma capacitance parameter [19] description test conditions 100-pin tqfp max 165-ball fbga max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 6.5 7 pf c clk clock input capacitance 3 7 pf c i/o input/output capacitance 5.5 6 pf thermal resistance parameter [19] description test conditions 100-pin tqfp package 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 25.21 20.8 c/w ? jc thermal resistance (junction to case) 2.28 3.2 c/w ac test loads and waveforms figure 3. ac test loads and waveforms electrical characteristics (continued) over the operating range parameter [17, 18] description test conditions min max unit output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1ns ? 1ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1ns ? 1ns (c) 3.3 v i/o test load 2.5 v i/o test load note 19. tested initially and after any design or process change that may affect these parameters.
cy7c1440av33 document number: 38-05383 rev. *k page 21 of 33 switching characteristics over the operating range parameter [20, 21] description -250 -167 unit min max min max t power v dd (typical) to the first access [22] 1?1?ms clock t cyc clock cycle time 4.0 ? 6 ? ns t ch clock high 1.5 ? 2.4 ? ns t cl clock low 1.5 ? 2.4 ? ns output times t co data output valid after clk rise ? 2.6 ? 3.4 ns t doh data output hold after clk rise 1.0 ? 1.5 ? ns t clz clock to low z [23, 24, 25] 1.0?1.5?ns t chz clock to high z [23, 24, 25] ? 2.6 ? 3.4 ns t oev oe low to output valid ? 2.6 ? 3.4 ns t oelz oe low to output low z [23, 24, 25] 0?0?ns t oehz oe high to output high z [23, 24, 25] ? 2.6 ? 3.4 ns set-up times t as address set-up before clk rise 1.2 ? 1.5 ? ns t ads adsc , adsp set-up before clk rise 1.2 ? 1.5 ? ns t advs adv set-up before clk rise 1.2 ? 1.5 ? ns t wes gw , bwe , bw x set-up before clk rise 1.2 ? 1.5 ? ns t ds data input set-up before clk rise 1.2 ? 1.5 ? ns t ces chip enable set-up before clk rise 1.2 ? 1.5 ? ns hold times t ah address hold after clk rise 0.3 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.3 ? 0.5 ? ns t advh adv hold after clk rise 0.3 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.3 ? 0.5 ? ns t dh data input hold after clk rise 0.3 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.3 ? 0.5 ? ns notes 20. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 21. test conditions shown in (a) of figure 3 on page 20 unless otherwise noted. 22. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 23. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in (b) of figure 3 on page 20 . transition is measured 200 mv from steady-state voltage. 24. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect pa rameters guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 25. this parameter is sampled and not 100% tested.
cy7c1440av33 document number: 38-05383 rev. *k page 22 of 33 switching waveforms figure 4. read cycle timing [26] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bwx data out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address don?t care undefined note 26. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high.
cy7c1440av33 document number: 38-05383 rev. *k page 23 of 33 figure 5. write cycle timing [27, 28] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x data out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined notes 27. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 28. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low.
cy7c1440av33 document number: 38-05383 rev. *k page 24 of 33 figure 6. read/write cycle timing [29, 30, 31] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw x data out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3 notes 29. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 30. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 31. gw is high.
cy7c1440av33 document number: 38-05383 rev. *k page 25 of 33 figure 7. zz mode timing [32, 33] switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 32. device must be deselected when entering zz mode. see cycle desc riptions table for all possible signal conditions to deselect the device. 33. dqs are in high z when exiting zz sleep mode.
cy7c1440av33 document number: 38-05383 rev. *k page 26 of 33 ordering code definitions ordering information cypress offers other versions of this type of product in diff erent configurations and features. the following table contains on ly the list of parts that are currently available. for a complete listing of all optio ns, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products , or contact your loca l sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 167 cy7c1440av33-167axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial 250 CY7C1440AV33-250AXC 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1440av33-250axi 100-pin tqfp (14 20 1.4 mm) pb-free industrial cy7c1440av33-250bzxi 51-85195 165-ball fbga (15 17 1.4 mm) pb-free temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or bz a = 100-pin tqfp bz = 165-ball fbga speed grade: 167 mhz or 250 mhz v33 = 3.3 v process technology: a ? 90 nm part identifier: 1440 = scd, 1 mb 36 (36 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 1440 a - xxx x xx v33 cy 7 x
cy7c1440av33 document number: 38-05383 rev. *k page 27 of 33 package diagrams figure 8. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1440av33 document number: 38-05383 rev. *k page 28 of 33 figure 9. 165-ball fbga (15 17 1.40 mm ) (0.50 ball diameter) package outline, 51-85195 package diagrams (continued) 51-85195 *c
cy7c1440av33 document number: 38-05383 rev. *k page 29 of 33 acronyms document conventions units of measure acronym description bga ball grid array ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group lsb least significant bit msb most significant bit nobl no bus latency oe output enable sram static random access memory tap test access port tck test clock tms test mode select tdi test data-in tdo test data-out tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere ms millisecond mm millimeter ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1440av33 document number: 38-05383 rev. *k page 30 of 33 document history page document title: cy7c1440av33, 36-mbit (1 m 36) pipelined sync sram document number: 38-05383 rev. ecn no. issue date orig. of change description of change ** 124437 03/04/03 cjm new data sheet. *a 254910 see ecn syt updated logic block diagram ? cy7c1440av33. updated logic block diagram ? cy7c1442av33. updated logic block diagram ? cy7c1446av33. updated identification register definitions (added note 14 and referred the same in device depth (28:24)). added boundary scan order related information. updated electrical characteristics (updated values of i dd , i x and i sb parameters). updated switching characteristics (added t power parameter and its details). updated switching waveforms . updated package diagrams (removed 119-ball pbga package, changed 165-ball fbga package from bb165c (15 17 1.20 mm) to bb165 (15 17 1.40 mm), cha nged 209-lead pbga bg209 (14 22 2.20 mm) to bb209a (14 22 1.76 mm)). *b 306335 see ecn syt updated pin configurations (changed h9 pin from v ssq to v ss for 209-ball fbga). updated thermal resistance (replaced ? ja and ? jc values from tbd to 25.21 ? c/w and 2.58 ? c/w respectively for 100-pin tqfp package, replaced ? ja and ? jc values from tbd to respective values for 165-ball fbga and 209-ball fbga packages). updated electrical characteristics (changed maximum value of i dd parameter from 450 ma, 400 ma, and 350 ma to 475 ma, 425 ma, and 375 ma for frequencies of 250 mhz, 200 mhz, and 167 mhz respectively, changed maximum value of i sb1 parameter from 190 ma, 180 ma, and 170 ma to 225 ma for frequencies of 250 mhz, 200 mhz, and 167 mhz respectively, changed maximum value of i sb2 from 80 ma to 100 ma, changed maximum value of i sb3 from 180 ma, 170 ma, and 160 ma to 200 ma for frequencies of 250 mhz, 200 mhz, and 167 mhz respectively, changed maximum value of i sb4 parameter from 100 ma to 110 ma). updated switching characteristics (changed maximum value of t co parameter from 3.0 ns to 3.2 ns for 200 mhz frequency, changed minimum value of t doh parameter from 1.3 ns to 1.5 ns for 200 mhz frequency). updated ordering information (added lead-free information for 100-pin tqfp, 165-ball fbga and 209-ball fbga packages). *c 332173 see ecn syt updated pin configurations (modified address expansion balls in the pinouts for 165-ball fbga and 209-ball fbga package as per jedec standards). updated operating range (added industrial temperature range). updated electrical characteristics (updated test conditions of v ol, v oh parameters, changed maximum value of i sb2 and i sb4 parameters from 100 ma and 110 ma to 120 ma and 135 ma respectively). updated capacitance (changed value of c in , c clk and c i/o to 7 pf, 7 pf, and 6 pf from 5 pf, 5 pf, and 7 pf for 165-ball fbga package). updated ordering information (by shading and unshading mpns as per availability). updated package diagrams (included 100-pin tqfp package diagram).
cy7c1440av33 document number: 38-05383 rev. *k page 31 of 33 *d 417547 see ecn rxu changed status from preliminary to final. changed address of cypress semicondu ctor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (updated note 18 (changed test condition from v ih < v dd to v ih ?? v dd ), changed ?input load cu rrent except zz and mode? to ?input leakage current except zz and mode? in the description of i x parameter, changed minimum value of i x corresponding to input current of mode (input = v ss ) from ?5 ? a to ?30 ? a, changed maximum value of i x corresponding to input cu rrent of mode (input = v dd ) from 30 ? a to 5 ? a respectively, changed minimum value of i x corresponding to input current of zz (input = v ss ) from ?30 ? a to ?5 ? a, changed maximum value of i x corresponding to input current of zz (input = v dd ) from 5 ? a to 30 ? a). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table). updated package diagrams . *e 473650 see ecn vkn updated tap ac switching characteristics (changed minimum value of t th , t tl parameters from 25 ns to 20 ns, changed maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *f 2897278 03/22/2010 njy updated ordering information (removed obsolete part numbers). updated package diagrams . *g 3044512 10/01/2010 njy added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *h 3055212 10/11/2010 njy updated ordering information (updated part numbers). *i 3357006 08/29/2011 prit updated package diagrams . updated in new template. *j 3424238 11/15/2011 prit updated ordering information (updated part numbers). updated package diagrams . document history page (continued) document title: cy7c1440av33, 36-mbit (1 m 36) pipelined sync sram document number: 38-05383 rev. ecn no. issue date orig. of change description of change
cy7c1440av33 document number: 38-05383 rev. *k page 32 of 33 *k 3616631 05/14/2012 prit updated features (removed 200 mhz frequency related information, removed cy7c1442av33, cy7c1446av33 related information, removed 209-ball fbga package related information). updated functional description (removed cy7c1442av33, cy7c1446av33 related information, removed the note ?for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com .? and its reference). updated selection guide (removed 200 mhz frequency related information). removed logic block diagram ? cy7c1442av33. removed logic block diagram ? cy7c1446av33. updated pin configurations (updated figure 1 (removed cy7c1442av33 related information), updated figure 2 (removed cy7c1442av33 related information), removed 209-ball fbga package related information). updated functional overview (removed cy7c1442av33, cy7c1446av33 related information). updated truth table (removed cy7c1442av33, cy7c1446av33 related information). removed truth table for read/write (corresponding to cy7c1442av33). removed truth table for read/write (corresponding to cy7c1446av33). updated ieee 1149.1 serial boundary scan (jtag) (removed cy7c1442av33, cy7c1446av33 related information). updated identification register definitions (removed cy7c1442av33, cy7c1446av33 related information). updated scan register sizes (removed ?bit size ( 18)?, ?bit size ( 72)? columns). updated boundary scan order (removed cy7c1442av33 related information). removed boundary scan order (corresponding to 209-ball fbga package). updated electrical characteristics (removed 200 mhz frequency related information). updated capacitance (removed 209-ball fbga package related information). updated thermal resistance (removed 209-ball fbga package related information). updated switching characteristics (removed 200 mhz frequency related information). updated package diagrams (removed 209-ball fbga package related information (spec 51-85167)). document history page (continued) document title: cy7c1440av33, 36-mbit (1 m 36) pipelined sync sram document number: 38-05383 rev. ecn no. issue date orig. of change description of change
document number: 38-05383 rev. *k revised may 14, 2012 page 33 of 33 i486 is a trademark, and intel and pentium are registered trademarks of intel corporation. powerpc is a trademark of ibm corpor ation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1440av33 ? cypress semiconductor corporation, 2003-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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